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a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 rev. 0 ad7904/AD7914/ad7924 4-channel, 1 msps, 8-/10-/12-bit adcs with sequencer in 16-lead tssop functional block diagram v in 3 t/h i/p mux sequencer control logic 8-/10-/12-bit successive approximation adc gnd sclk dout din cs v drive v dd ad7904/AD7914/ad7924 ref in v in 0 features fast throughput rate: 1 msps specified for v dd of 2.7 v to 5.25 v low power: 6 mw max at 1 msps with 3 v supplies 13.5 mw max at 1 msps with 5 v supplies 4 (single-ended) inputs with sequencer wide input bandwidth: ad7924, 70 db snr at 50 khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface spi tm /qspi tm / microwire tm /dsp compatible shutdown mode: 0.5 a max 16-lead tssop package general description the ad7904/AD7914/ad7924 are respectively, 8-bit, 10-bit, and 12-bit, high speed, low power, 4-channel, successive-approxi- mation adcs. the parts operate from a single 2.7 v to 5.25 v power supply and feature throughput rates up to 1 msps. the parts contain a low noise, wide bandwidth track/hold amplifier that can handle input frequencies in excess of 8 mhz. the conversion process and data acquisition are controlled using cs and the serial clock signal, allowing the device to easily interface with microprocessors or dsps. the input signal is sampled on the falling edge of cs and conversion is also initiated at this point. there are no pipeline delays associated with the part. the ad7904/AD7914/ad7924 use advanced design techniques to achieve very low power dissipation at maximum throughput rates. at maximum throughput rates, the ad7904/AD7914/ad7924 consume 2 ma maximum with 3 v supplies; with 5 v supplies, the current consumption is 2.7 ma maximum. through the configuration of the control register, the analog input range for the part can be selected as 0 v to ref in or 0 v to 2 ref in , with either straight binary or twos complement output coding. the ad7904/AD7914/ad7924 each feature four single-ended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequentially. the conversion time for the ad7904/AD7914/ad7924 is deter- mined by the sclk frequency, as this is also used as the master clock to control the conversion. product highlights 1. high throughput with low power consumption. the ad7904/AD7914/ad7924 offer up to 1 msps through- put rates. at the maximum throughput rate with 3 v sup`plies, the ad7904/AD7914/ad7924 dissipate just 6 mw of power maximum. 2. four single-ended inputs with a channel sequencer. a consecutive sequence of channels can be selected, through which the adc will cycle and convert on. 3. single-supply operation with v drive function. the ad7904/AD7914/ad7924 operate from a single 2.7 v to 5.25 v supply. the v drive function allows the serial inter- face to connect directly to either 3 v or 5 v processor systems independent of v dd . 4. flexible power/serial clock speed management. the conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. the parts also feature various shutdown modes to maximize power efficiency at lower throughput rates. current consumption is 0.5 a max when in full shutdown. 5. no pipeline delay. the parts feature a standard successive-approximation adc with accurate control of the sampling instant via a cs input and once off conversion control. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation.
?2? rev. 0 (av dd = v drive = 2.7 v to 5.25 v, ref in = 2.5 v, f sclk = 20 mhz, t a = t min to t max , unless otherwise noted.) ad7904 C
ad7904/AD7914/ad7924 ?3? rev. 0 parameter b version 1 unit test conditions/comments power requirements v dd 2.7/5.25 v min/max v drive 2.7/5.25 v min/max i dd 4 digital i/ps = 0 v or v drive normal mode (static) 600 a typ v dd = 2.7 v to 5.25 v, sclk on or off normal mode (operational) 2.7 ma max v dd = 4.75 v to 5.25 v, f sclk = 20 mhz 2 ma max v dd = 2.7 v to 3.6 v, f sclk = 20 mhz using auto shutdown mode 960 a typ f sample = 250 ksps 0.5 a max (static) full shutdown mode 0.5 a max sclk on or off (20 na typ) power dissipation 4 normal mode (operational) 13.5 mw max v dd = 5 v, f sclk = 20 mhz 6 mw max v dd = 3 v, f sclk = 20 mhz auto shutdown mode (static) 2.5 w max v dd = 5 v 1.5 w max v dd = 3 v full shutdown mode 2.5 w max v dd = 5 v 1.5 w max v dd = 3 v notes 1 temperature ranges as follows: b version: e40 c to +85 c. 2 see terminology section. 3 sample tested @ 25 c to ensure compliance. 4 see power versus throughput rate section. specifications subject to change without notice.
?4? rev. 0 parameter b version 1 unit test conditions/comments dynamic performance f in = 50 khz sine wave, f sclk = 20 mhz signal-to-noise + distortion (sinad) 2 61 db min signal-to-noise ratio (snr) 2 61 db min total harmonic distortion (thd) 2 e72 db max peak harmonic or spurious noise (sfdr) 2 e74 db max intermodulation distortion (imd) 2 fa = 40.1 khz, fb = 41.5 khz second order terms e90 db typ third order terms e90 db typ aperture delay 10 ns typ aperture jitter 50 ps typ channel-to-channel isolation 2 e85 db typ f in = 400 khz full power bandwidth 8.2 mhz typ @ 3 db 1.6 mhz typ @ 0.1 db dc accuracy 2 resolution 10 bits integral nonlinearity 0.5 lsb max differential nonlinearity 0.5 lsb max guaranteed no missed codes to 10 bits 0 v to ref in input range straight binary output coding offset error 2lsb max offset error match 0.2 lsb max gain error 0.5 lsb max gain error match 0.2 lsb max 0 v to 2 ref in input range eref in to +ref in biased about ref in w ith positive gain error 0.5 lsb max twos complement output coding positive gain error match 0.2 lsb max zero code error 2lsb max zero code error match 0.2 lsb max negative gain error 0.5 lsb max negative gain error match 0.2 lsb max analog input input voltage range 0 to ref in v range bit set to 1 0 to 2 ref in v range bit set to 0, v dd /v drive = 4.75 v to 5.25 v dc leakage current 1 a max input capacitance 20 pf typ reference input ref in input voltage 2.5 v 1% specified performance dc leakage current 1 a max ref in input impedance 36 k typ f sample = 1 msps logic inputs input high voltage, v inh 0.7 v drive v min input low voltage, v inl 0.3 v drive v max input current, i in 1 a max typically 10 na, v in = 0 v or v drive input capacitance, c in 3 10 pf max logic outputs output high voltage, v oh v drive e 0.2 v min i source = 200 a, v dd = 2.7 v to 5.25 v output low voltage, v ol 0.4 v max i sink = 200 a floating-state leakage current 1 a max floating-state output capacitance 3 10 pf max output coding straight (natural) binary coding bit set to 1 twos complement coding bit set to 0 conversion rate conversion time 800 ns max 16 sclk cycles with sclk at 20 mhz track/hold acquisition time 300 ns max sine wave input 300 ns max full-scale step input throughput rate 1 msps max see serial interface section (av dd = v drive = 2.7 v to 5.25 v, ref in = 2.5 v, f sclk = 20 mhz, t a = t min to t max , unless otherwise noted.) AD7914 C
ad7904/AD7914/ad7924 ?5? rev. 0 parameter b version 1 unit test conditions/comments power requirements v dd 2.7/5.25 v min/max v drive 2.7/5.25 v min/max i dd 4 digital i/ps = 0 v or v drive normal mode (static) 600 a typ v dd = 2.7 v to 5.25 v, sclk on or off normal mode (operational) 2.7 ma max v dd = 4.75 v to 5.25 v, f sclk = 20 mhz 2 ma max v dd = 2.7 v to 3.6 v, f sclk = 20 mhz using auto shutdown mode 960 a typ f sample = 250 ksps 0.5 a max (static) full shutdown mode 0.5 a max sclk on or off (20 na typ) power dissipation 4 normal mode (operational) 13.5 mw max v dd = 5 v, f sclk = 20 mhz 6 mw max v dd = 3 v, f sclk = 20 mhz auto shutdown mode (static) 2.5 w max v dd = 5 v 1.5 w max v dd = 3 v full shutdown mode 2.5 w max v dd = 5 v 1.5 w max v dd = 3 v notes 1 temperature ranges as follows: b version: e40 c to +85 c. 2 see terminology section. 3 sample tested @ 25 c to ensure compliance. 4 see power versus throughput rate section. specifications subject to change without notice.
?6? rev. 0 (av dd = v drive = 2.7 v to 5.25 v, ref in = 2.5 v, f sclk = 20 mhz, t a = t min to t max , unless otherwise noted.) ad7924 C
ad7904/AD7914/ad7924 ?7? rev. 0 parameter b version 1 unit test conditions/comments conversion rate conversion time 800 ns max 16 sclk cycles with sclk at 20 mhz track/hold acquisition time 300 ns max sine wave input 300 ns max full-scale step input throughput rate 1 msps max see serial interface section power requirements v dd 2.7/5.25 v min/max v drive 2.7/5.25 v min/max i dd 4 digital i/ps = 0 v or v drive normal mode(static) 600 a typ v dd = 2.7 v to 5.25 v, sclk on or off normal mode (operational) 2.7 ma max v dd = 4.75 v to 5.25 v, f sclk = 20 mhz 2 ma max v dd = 2.7 v to 3.6 v, f sclk = 20 mhz using auto shutdown mode 960 a typ f sample = 250 ksps 0.5 a max (static) full shutdown mode 0.5 a max sclk on or off (20 na typ) power dissipation 4 normal mode (operational) 13.5 mw max v dd = 5 v, f sclk = 20 mhz 6 mw max v dd = 3 v, f sclk = 20 mhz auto shutdown mode (static) 2.5 w max v dd = 5 v 1.5 w max v dd = 3 v full shutdown mode 2.5 w max v dd = 5 v 1.5 w max v dd = 3 v notes 1 temperature ranges as follows: b versions: e40 c to +85 c. 2 see terminology section. 3 sample tested @ 25 c to ensure compliance. 4 see power versus throughput rate section. specifications subject to change without notice.
? ad7904/AD7914/ad7924 rev. 0 timing specifications 1 (v dd = 2.7 v to 5.25 v, v drive v dd , ref in = 2.5 v, t a = t min to t max , unless otherwise noted.) limit at t min , t max ad7904/AD7914/ad7924 parameter v dd = 3 v v dd = 5 v unit description f sclk 2 10 10 khz min 20 20 mhz max t convert 16 t sclk 16 t sclk t quiet 50 50 ns min minimum quiet time required between cs rising edge and start of next conversion t 2 10 10 ns min cs to sclk setup time t 3 3 35 30 ns max delay from cs until dout three-state disabled t 4 3 40 40 ns max data access time after sclk falling edge t 5 0.4 t sclk 0.4 t sclk ns min sclk low pulsewidth t 6 0.4 t sclk 0.4 t sclk ns min sclk high pulsewidth t 7 10 10 ns min sclk to dout valid hold time t 8 4 15/45 15/35 ns min/max sclk falling edge to dout high impedance t 9 10 10 ns min din setup time prior to sclk falling edge t 10 55 ns min din hold time after sclk falling edge t 11 20 20 ns min sixteenth sclk falling edge to cs h igh t 12 11 s ma x power-up time from full power-down/auto shutdown modes notes 1 sample tested at 25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. see figure 1. the 3 v operating range spans from 2.7 v to 3.6 v. the 5 v operating range spans from 4.75 v to 5.25 v. 2 mark/space ratio for the sclk input is 40/60 to 60/40. 3 measured with the load circuit of figure 1 and defined as the time required for the output to cross 0.4 v or 0.7 v drive . 4 t 8 is derived form the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 8 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. specifications subject to change without notice.
ad7904/AD7914/ad7924 ?9? rev. 0 absolute maximum ratings 1 (t a = 25 c unless otherwise noted.) av dd to agnd ............................................... e0.3 v to +7 v v drive to agnd ................................ e0.3 v to av dd + 0.3 v analog input voltage to agnd ......... e0.3 v to av dd + 0.3 v digital input voltage to agnd ........................ e0.3 v to +7 v digital output voltage to agnd ........... e0.3 v to av dd + 0.3 v ref in to agnd ................................ e0.3 v to av dd + 0.3 v input current to any pin except supplies 2 ................. 10 ma operating temperature range commercial (b version) ............................. e40 c to +85 c storage temperature r ange ...................... e65 c to +150 c junction temperature ................................................... 150 c to output pin c l 50pf 200 a i oh 200 a i ol 1.6v figure 1. load circuit for digital output timing specifications ordering guide temperature linearity package package model range error (lsb) 1 option description ad7904bru e40 c to +85 c 0.2 ru-16 tssop AD7914bru e40 c to +85 c 0.5 ru-16 tssop ad7924bru e40 c to +85 c 1 ru-16 tssop eval-ad79x4cb 2 evaluation board eval-control brd2 3 controller board notes 1 linearity error here refers to integral linearity error. 2 this can be used as a stand alone evaluation board or in conjunction with the evaluation controller board for evaluation/demons tration purposes. the board comes with one chip of each the ad7904, AD7914, and ad7924. 3 this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. to order a complete evaluation kit you will need to order the particular adc evaluation board, e.g., eval-ad79x4cb, the eval-contr ol brd2, and a 12 v ac transformer. see relevant evaluation board technical note for more information. tssop package, power d issipation ........................... 450 mw ja thermal impedance ......................... 150.4 c/w (tssop) jc thermal impedance ........................... 27.6 c/w (tssop) lead temperature, soldering vapor phase (60 secs) ................................................ 215 c infrared (15 secs) ....................................................... 220 c esd ................................................................................. 2 kv notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch up. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7904/AD7914/ad7924 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
?10? ad7904/AD7914/ad7924 rev. 0 pin function descriptions pin no. mnemonic function 1 sclk serial clock. logic input. sclk provides the serial clock for accessing data from the part. this clock input is also used as the clock source for the ad7904/AD7914/ad7924?s conversion process. 2d in data in. logic input. data to be written to the ad7904/AD7914/ad7924?s control register is provided on this input and is clocked into the register on the falling edge of sclk (see control register section). 3 cs chip select. active low logic input. this input provides the dual function of initiating conversions on the ad7904/AD7914/ad7924 and also frames the serial data transfer. 4, 8, 13, 16 agnd analog ground. ground reference point for all analog circuitry on the ad7904/AD7914/ad7924. all analog input signals and any external reference signal should be referred to this agnd voltage. all agnd pins should be connected together. 5, 6 av dd analog power supply input. the av dd range for the ad7904/AD7914/ad7924 is from 2.7 v to 5.25 v. for the 0 v to 2 ref in range, av dd should be from 4.75 v to 5.25 v. 7 ref in reference input for the ad7904/AD7914/ad7924. an external reference must be applied to this input. the voltage range for the external reference is 2.5 v 1% for specified performance. 12e9 v in 0ev in 3a nalog input 0 through analog input 3. four single-ended analog input channels that are multiplexed into the on-chip track/hold. the analog input channel to be converted is selected by using the address bits add1 and add0 of the control register. the address bits, in conjunction with the seq1 and seq0 bits, allow the sequencer to be programmed. the input range for all input channels can extend from 0 v to ref in or 0 v to 2 ref in as selected via the range bit in the control register. any unused input channels should be connected to agnd to avoid noise pickup. 14 dout data out. logic output. the conversion result from the ad7904/AD7914/ad7924 is provided on this output as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream from the ad7904 consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the eight bits of conversion data, followed by four trailing zeros, provided msb first; the data stream from the AD7914 consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the 10 bits of conversion data, followed by two trailing zeros, also provided msb first; the data stream from the ad7924 consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data provided msb first. the output coding may be selected as straight binary or twos complement via the coding bit in the control register. 15 v drive logic power supply input. the voltage supplied at this pin determines what voltage the serial interface of the ad7904/AD7914/ad7924 will operate at. pin configuration 16-lead tssop 1 ad7904/ AD7914/ ad7924 sclk agnd 16 top view (not to scale) 2 din v drive 15 3 cs dout 14 4 a gnd agnd 13 5 av dd v in 0 12 6 av dd v in 1 11 7 ref in v in 2 10 8 a gnd v in 3 9
ad7904/AD7914/ad7924 ?11? rev. 0 terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the end- points of the transfer function are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., agnd + 1 lsb. offset error match this is the difference in offset error between any two channels. gain error this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., ref in e 1 lsb) after the offset error has been adjusted out. gain error match this is the difference in gain error between any two channels. zero code error this applies when using the twos complement output coding option, in particular to the 2 ref in input range with eref in to +ref in biased about the ref in point. it is the deviation of the midscale transition (all 0s to all 1s) from the ideal v in volt- age, i.e., ref in e 1 lsb. zero code error match this is the difference in zero code error between any two channels. positive gain error this applies when using the twos complement output coding option, in particular to the 2 ref in input range with eref in to +ref in biased about the ref in point. it is the deviation of the last code transition (011. . .110) to (011 . . . 111) from the ideal (i.e., +ref in e 1 lsb) after the zero code error has been adjusted out. positive gain error match this is the difference in positive gain error between any two channels. negative gain error this applies when using the twos complement output coding option, in particular to the 2 ref in input range with eref in to +ref in biased about the ref in point. it is the deviation of the first code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e., eref in + 1 lsb) after the zero code error has been adjusted out. negative gain error match this is the difference in negative gain error between any two channels. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a full-scale 400 khz sine wave signal to all three nonselected input channels and deter- mining how much that signal is attenuated in the selected channel with a 50 khz signal. the figure is given worst case across all four channels for the ad7904/AD7914/ad7924. psr (power supply rejection) variations in power supply will affect the full scale transition, but not the converter?s linearity. power supply rejection is the maximum change in full-scale transition point due to a change in power-supply voltage from the nominal value. see typical performance curves. track/hold acquisition time the track/hold amplifier returns into track mode at the end of conversion. track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1 lsb, after the end of conversion. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental sig- nals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantiza- tion noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to noise distortion n db ()(..) +=+ thd db vvvvv v () log = ++++ v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics.
?12? ad7904/AD7914/ad7924 C psrr db pf pfs () log( / ) = pf is equal to the power at frequency f in adc output; pf s is equal to the power at frequency f s coupled onto the adc av dd supply. here a 200 mv p-p sine wave is coupled onto the av dd supply. tpc 4 shows a graph of total harmonic distortion versus analog input frequency for various supply voltages, while tpc 5 shows a graph of total harmonic distortion versus analog input frequency for various source impedances. see the analog input section. tpc 6 and tpc 7 show typical inl and dnl plots for the ad7924. frequency e khz e10 0 100 200 300 400 500 snr e db e30 e50 e70 e90 e110 50 150 250 350 450 4096 point fft v dd = 5v f sample = 1msps f in = 50khz sinad = 71.147 thd = e87.229 sfdr = e90.744 tpc 1. ad7924 dynamic performance at 1 msps input frequency e khz 75 10 1000 sinad e db 70 65 60 55 100 f sample = 1msps t a = 25 c range = 0 to ref in v dd = v drive = 2.7v v dd = v drive = 3.6v v dd = v drive = 4.75v v dd = v drive = 5.25v tpc 2. ad7924 sinad vs. analog input frequency for various supply voltages at 1 msps supply ripple frequency e khz 0 0 1000 psrr e db e40 e60 e80 e90 500 e20 e50 e70 900 800 700 600 400 300 200 100 v dd = 5v, 200mv p-p sine wave on v dd ref in = 2.5v, 1 f capacitor t a = 25 c e10 e30 tpc 3. ad7924 psrr vs. supply ripple frequency input frequency e khz e50 10 1000 thd e db e65 e75 e85 e90 e60 e70 e80 100 e55 v dd = v drive = 5.25v v dd = v drive = 4.75v v dd = v drive = 3.6v v dd = v drive = 2.7v f sample = 1msps t a = 25 c range = 0 to ref in tpc 4. ad7924 thd vs. analog input frequency for various supply voltages at 1 msps input frequency e khz e50 10 1000 thd e db e65 e75 e85 e90 e60 e70 e80 100 e55 f sample = 1msps t a = 25 c range = 0 to ref in v dd = 5.25v r in = 10 r in = 50 r in = 100 r in = 1000 tpc 5. ad7924 thd vs. analog input frequency for various source impedances
ad7904/AD7914/ad7924 ?13? rev. 0 table i. control register bit functions msb lsb write seq1 dontc dontc add1 add0 pm1 pm0 seq0 dontc range coding bit mnemonic comment 11 write the value written to this bit of the control register determines whether the following 11 bits will be loaded to the control register or not. if this bit is a 1 then the following 11 bits will be written to the control register; if it is a 0 then the remaining 11 bits are not loaded to the control register and so it remains unchanged. 10 seq1 the seq1 bit in the control register is used in conjunction with the seq0 bit to control the use of the sequencer function. (see table iv.) 9e8 dontcare 7e6 add1, add0 these two address bits are loaded at the end of the present conversion sequence and select which analog input channel is to be converted in the next serial transfer, or they may select the final channel in a consecutive sequence as described in table iv. the selected input channel is decoded as shown in table ii. the address bits corresponding to the conversion result are also output on dout prior to the 12 bits of data, see the serial interface section. the next channel to be converted on will be selected by the mux on the fourteenth sclk falling edge. 5, 4 pm1, pm0 power management bits. these two bits decode the mode of operation of the ad7904/AD7914/ad7924 as shown in table iii. 3 seq0 the seq0 bit in the control register is used in conjunction with the seq1 bit to control the use of the sequencer function. (see table iv.) 2 dontcare 1 range this bit selects the analog input range to be used on the ad7904/AD7914/ad7924. if it is set to 0 then the analog input range will extend from 0 v to 2 ref in . if it is set to 1 then the an alog input range will extend from 0 v to ref in (for the next conversion). for 0 v to 2 ref in , v dd = 4.75 v to 5.25 v. 0 coding this bit selects the type of output coding the ad7904/AD7914/ad7924 will use for the conversion result. if this bit is set to 0 the output coding for the part will be twos complement. if this bit is set to 1 then the output coding from the part will be straight binary (for the next conversion). code 1.0 0 4096 inl error e lsb 0 e0.4 e0.8 e1.0 0.2 e0.2 e0.6 2048 0.6 v dd = v drive = 5v temp = 25 c 0.4 0.8 2560 3072 3584 512 1024 1536 tpc 6. ad7924 typical inl control register the control register on the ad7904/AD7914/ad7924 is a 12-bit, write-only register. data is loaded from the din pin of the ad7904/AD7914/ad7924 on the falling edge of sclk. the data is transferred on the din line at the same time that the conver- sion result is read from the part. the data transferred on the din line corresponds to the ad7904/AD7914/ad7924 configuration for the next conversion. this requires 16 serial clocks for every data transfer. only the information provided on the first 12 falling clock edges (after cs falling edge) is loaded to the control register. msb denotes the first bit in the data stream. the bit functions are outlined in table i. code 1.0 0 4096 dnl error e lsb 0 e0.4 e0.8 e1.0 0.2 e0.2 e0.6 2048 0.6 0.4 0.8 2560 3072 3584 512 1024 1536 v dd = v drive = 5v temp = 25 c tpc 7. ad7924 typical dnl
?4 ad7904/AD7914/ad7924 rev. 0 table ii. channel selection add1 add0 analog input channel 00 v in 0 01 v in 1 10 v in 2 11 v in 3 table iii. power mode selection pm1 pm0 mode 11 normal operation . in this mode, the ad7904/ AD7914/ad7924 remain in full power mode regardless of the status of any of the logicinputs. this mode allows the fastest possible throughput rate from the ad7904/AD7914/ad7924. 10 full shutdown . in this mode, the ad7904/ AD7914/ad7924 is in full shutdown mode with all circuitry on the ad7904/AD7914/ad7924 powering down. the ad7904/AD7914/ad7924 retains the information in the control register while in full shutdown. the part remains in full shutdown until these bits are changed. 01 auto shutdown . in this mode, the ad7904/ AD7914/ad7924/ automatically enters full shutdown mode at the end of each conversion when the control register is updated. wake-up time from full shutdown is 1 s and the user should ensure that 1 s has elapsed before attempting to perform a valid conversion on the part in this mode. 00 invalid se lection . thi s configuration is not all owed. sequencer operation the configuration of the seq1 and seq0 bits in the control register allows the user to select a particular mode of operation of the sequencer function. table iv outlines the three modes of operation of the sequencer. figure 2 reflects the traditional operation of a multichannel adc, where each serial transfer selects the next channel for conversion. in this mode of operation the sequencer function is not used. figure 3 shows how to program the ad7904/AD7914/ad7924 to continuously convert on a sequence of consecutive channels from channel 0 to a selected final channel. to exit this mode of operation and revert back to the traditional mode of operation of a multichannel adc (as outlined in figure 2), ensure that the write bit = 1 and seq1 = seq0 = 0 on the next serial transfer. table iv. sequence selection seq1 seq0 sequence type 0x this configuration means that the sequence function is not used. the analog input channel selected for each individual conversion is determined by the contents of the channel address bits add1, add0 in each prior write operation. this mode of operation reflects the traditional operation of a multichannel adc, without the sequencer function being used, where each write to the ad7904/AD7914/ad7924 selects the next channel for conversion (see figure 2). 10 if the seq1 and seq0 bits are set in this way then the sequence function will not be interrupted upon completion of the write operation. this allows other bits in the control register to be altered between conversions while in a sequence without terminating the cycle. 11 this configuration is used in conjunction with the channel address bits add1, add0 to program continuous conversions on a consecutive sequence of channels from channel 0 to a selected final channel as determined by the channel address bits in the control register (see figure 3).
ad7904/AD7914/ad7924 ?15? rev. 0 power on dummy conversion din: write to control register, write bit = 1, select coding, range, and power mode. select channel a1, a0 for conversion. seq1 = 0, seq0 = x dout: conversion result from previously selected channel a1, a0 din: write to control register, write bit = 1, select coding, range, and power mode. select a1, a0 for conversion. seq1 = 0, seq0 = x write bit = 1, seq1 = 0, seq0 = x cs cs figure 2. seq1 bit = 0, seq0 bit = x flowchart power on dummy conversion din: write to control register, write bit = 1, select coding, range, and power mode. select channel a1, a0 for conversion. seq1 = 1, seq0 = 1 dout: conversion result from channel 0 continuously converts on a consecutive sequence of channels from channel 0 up to and including the previously selected a1, a0 in the control register write bit = 0 continuously converts on the selected sequence of channels but will allow range, coding, and so forth, to change in the control register without interrupting the sequence, provided seq1 = 1, seq0 = 0 write bit = 1, seq1 = 1, seq0 = 0 cs cs cs figure 3. seq1 bit = 1, seq0 bit = 1 flowchart circuit information the ad7904/AD7914/ad7924 are high speed, 4-channel, 8-bit, 10-bit, and 12-bit, single supply, a/d converters, respectively. the parts can be operated from a 2.7 v to 5.25 v supply. when operated from either a 5 v or 3 v supply, the ad7904/AD7914/ ad7924 are capable of throughput rates of 1 msps when pro- vided w ith a 20 mhz clock. the ad7904/AD7914/ad7924 provide the user with an on-chip track/hold, a/d converter, and a serial interface housed in a 16- lead tssop package. the ad7904/AD7914/ad7924 each have four single-ended input channels with a channel sequencer, allowing the user to select a channel sequence through which the adc can cycle with each consecutive cs falling edge. the serial clock input accesses data from the part, controls the transfer of data written to the adc, and provides the clock source for the successive-approximation a/d converter. the analog input range for the ad7904/AD7914/ad7924 is 0 v to ref in or 0 v to 2 ref in , depending on the status of bit 1 in the control register. for the 0 to 2 ref in range, the part must be operated from a 4.75 v to 5.25 v supply. the ad7904/AD7914/ad7924 provide flexible power management options to allow the user to achieve the best power performance for a given throughput rate. these options are selected by programming the power management bits, pm1 and pm0, in the control register. converter operation the ad7904/AD7914/ad7924 are 8-, 10-, and 12-bit successive approximation analog-to-digital converters based around a capacitive dac, respectively. the ad7904/AD7914/ad7924 can convert analog input signals in the range 0 v to ref in or 0 v to 2 ref in . figures 4 and 5 show simplified schematics of the adc. the adc is comprised of control logic, sar, and a capacitive dac, which are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. figure 4 shows the adc during its acquisition phase. sw2 is closed and sw1 is in position a. the comparator is held in a balanced condition and the sampling capacitor acquires the signal on the selected v in channel. v in 0 v in 3 a gnd a b sw1 sw2 comparator control logic capacitive dac 4k figure 4. adc acquisition phase
?16? ad7904/AD7914/ad7924 rev. 0 when the adc starts a conversion (see figure 5), sw2 will open and sw1 will move to position b, causing the comparator to become unbalanced. the control logic and the capacitive dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. figures 7 and 8 show the adc transfer functions. v in 0 . . v in 3 a gnd a b sw1 sw2 comparator control logic 4k capacitive dac figure 5. adc conversion phase analog input figure 6 shows an equivalent circuit of the analog input structure of the ad7904/AD7914/ad7924. the two diodes d1 and d2 provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mv. this will cause these diodes to become forward biased and start conducting current into the substrate. 10 ma is the maximum current these diodes can conduct without causing irreversible damage to the part. the capacitor c1 in figure 6 is typically about 4 pf and can primarily be attributed to pin capacitance. the resistor r1 is a lumped com- ponent made up of the on resistance of a switch (track and hold switch) and also includes the on resistance of the input multiplexer. the total resistance is typically about 400 . the capacitor c2 is the adc sampling capacitor and has a capacitance of 30 pf typically. for ac applications, removing high frequency compo- nents from the analog input signal is recommended by use of an rc low-pass filter on the relevant analog input pin. in applica- tions where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances will significantly affect the ac performance of the adc. this may necessitate the use of an input buffer amplifier. the choice of the op amp will be a function of the particular application. when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance will depend on the amount of total harmonic distortion (thd) that can be tolerated. the thd will increase as the source impedance increases and performance will degrade (see tpc 5). v in c1 4pf c2 30pf r1 d1 d2 v dd conversion phase: switch open track phase: switch closed figure 6. equivalent analog input circuit adc transfer function the output coding of the ad7904/AD7914/ad7924 is either straight binary or twos complement, depending on the status of the lsb in the control register. the designed code transitions occur at successive lsb values (i.e., 1 lsb, 2 lsbs, and so on). the lsb size is ref in /256 for the ad7904 , ref in /1024 for the AD7914, and ref in /4096 for the ad7924. the ideal transfer characteristic for the ad7904/AD7914/ad7924 when straight binary coding is selected is shown in figure 7, and the ideal transfer characteristic for the ad7904/AD7914/ad7924 when twos complement coding is selected is shown in figure 8. 000000 0v analog input 111111 000001 000010 111110 111000 011111 1 lsb +v ref 1 lsb 1lsb = v ref /256 ad7904 1lsb = v ref /1024 AD7914 1lsb = v ref /4096 ad7924 note: v ref is either ref in or 2 ref in figure 7. straight binary transfer characteristic ev ref 1 lsb adc code analog input +v ref 1 lsb 1lsb = 2 v ref 256 ad7904 1lsb = 2 v ref 1024 AD7914 1lsb = 2 v ref 4096 ad7924 v ref 1 lsb 100000 011111 100001 100010 011110 000001 111111 000000 figure 8. twos complement transfer characteristic with ref in ref in input range handling bipolar input signals figure 9 shows how useful the combination of the 2 ref in input range and the twos complement output coding scheme is for handling bipolar input signals. if the bipolar input signal is biased about ref in and twos complement output coding is selected, then ref in becomes the zero code point, eref in is negative full scale and +ref in becomes positive full scale, with a dynamic range of 2 ref in . typical connection diagram figure 10 shows a typical connection diagram for the ad7904/ AD7914/ad7924. in this setup the gnd pin is connected to the analog ground plane of the system. in figure 10, ref in is connected to a decoupled 2.5 v supply from a reference source, the ad780, to provide an analog input range of 0 v to 2.5 v (if range bit is 1) or 0 v to 5 v (if range bit is 0). although the ad7904/AD7914/ad7924 is connected to a v dd of 5 v, the serial interface is connected to a 3 v microprocessor. the v drive pin of the ad7904/AD7914/ad7924 is connected to the same 3 v supply of the microprocessor to allow a 3 v logic interface (see the digital inputs section). the conversion result is output in a
ad7904/AD7914/ad7924 ?17? rev. 0 16-bit word. this 16-bit data stream consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data for the ad7924 (10 bits of data for the AD7914 and 8 bits of data for the ad7904, each followed by 2 and 4 trailing zeros, respec- tively). for appli cations where power consumption is of concern, the power-down m odes should be used between conversions or bursts of several conversions to improve power performance. see the modes of operation section of the data sheet. serial interface ad780 2.5v ad7904/ AD7914/ ad7924 0.1 f c/ p 0.1 f 10 f 3v supply 5v supply 0.1 f 10 f a gnd v dd v in 0 v in 3 0v to ref in sclk dout cs din v drive ref in note: all unused input channels should be connected to agnd figure 10. typical connection diagram analog input selection any one of four analog input channels may be selected for con- version by programming the multiplexer with the address bits add1 and add0 in the control register. the channel con- figurations are shown in table ii. the ad7904/AD7914/ad7924 may also be configured to auto- matically cycle through a number of channels as selected. the sequencer feature is accessed via the seq1 and seq0 bits in the control register, see table iv. the ad7904/AD7914/ad7924 can be programmed to continuously convert on a number of consecutive channels in ascending order from channel 0 to a selected final channel as determined by the channel address bits add1 and add0. this is possible if the seq1 and seq0 bits are set to 1,1. the next serial transfer will then act on the sequence programmed by executing a conversion on channel 0. the next serial transfer will result in a conversion on channel 1, and so on, until the channel selected via the address bits add1, add0 is reached. it is not necessary to write to the control register again once a sequencer operation has been initiated. the write bit must be set to zero or the din line tied low to ensure the control regis- ter is not accidently overwritten, or the sequence operation interrupted. if the control register is written to at any time during the sequence then it must be ensured that the seq1 and seq0 bits are set to 1,0 to avoid interrupting the automatic conversion sequence. this pattern will continue until such time as the ad7904/AD7914/ad7924 is written to and the seq1 and seq0 bits are configured with any bit combination except 1,0 resulting in the termination of the sequence. if uninter- rupted, however (write bit = 0, or write bit = 1 and seq1 and seq0 bits are set to 1,0), then upon completion of the sequence, the ad7904/AD7914/ad7924 sequencer will return to the channel 0 and commence the sequence again. regardless of which channel selection method is used, the 16-bit word output from the ad7924 during each conversion will always contain two leading zeros, two channel address bits that the con- version result corresponds to, followed by the 12-bit conversion result; the AD7914 will output two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 10-bit conversion result and two trailing zeros; the ad7904 will output two leading zeros, two channel address bits that the conver- sion result corresponds to, followed by the 8-bit conversion result and four trailing zeros. see the serial interface section. digital inputs the digital inputs applied to the ad7904/AD7914/ad7924 are not limited by the maximum ratings that limit the analog inputs. instead, the digital inputs applied can go to 7 v and are not restricted by the v dd + 0.3 v limit as on the analog inputs. another advantage of sclk, din, and cs not being restricted by the v dd + 0.3 v limit is the fact that power supply sequenc- ing issues are avoided. if cs , din, or sclk are applied before v dd there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 v was applied prior to v dd . v drive the ad7904/AD7914/ad7924 also have the v drive feature. v drive controls the voltage at which the serial interface oper- ates. v drive allows the adc to easily interface to both 3 v and 5 v processors. for example, if the ad7904/AD7914/ad7924 were operated with a v dd of 5 v, the v drive pin could be pow- ered from a 3 v supply. the ad7904/AD7914/ad7924 have r3 r2 r4 ref in v in 0 v in 3 ad7904/ AD7914/ ad7924 dsp/ p v dd 0.1 f v v dd v drive dout twos complement +ref in ref in eref in 011111 000000 100000 (= 0v) (= 2 ref in ) 0v v r1 r1 r2 r3 r4 v dd v ref figure 9. handling bipolar signals
?18? ad7904/AD7914/ad7924 rev. 0 better dynamic performance with a v dd of 5 v while still being able to interface to 3 v processors. care should be taken to ensure v drive does not exceed v dd by more than 0.3 v. (see the absolute maximum ratings section). r eference an external reference source should be used to supply the 2.5 v reference to the ad7904/AD7914/ad7924. errors in the refer- ence source will result in gain errors in the ad7904/AD7914/ ad7924 transfer function and will add to the specified full-scale errors of the part. a capacitor of at least 0.1 f should be placed on the ref in pin. suitable reference sources for the ad7904/ AD7914/ad7924 include the ad780, ref 193, and the ad1582. if 2.5 v is applied to the ref in pin, the analog input range can either be 0 v to 2.5 v or 0 v to 5 v, depending on the setting of the range bit in the control register. modes of operation the ad7904/AD7914/ad7924 have a number of different modes of operation. these modes are designed to provide flex- ible power management options. these options can be chosen to optimize the power dissipation/throughput rate ratio for dif- fering application requirements. the mode of operation of the ad7904/AD7914/ad7924 is controlled by the power manage- ment bits, pm1 and pm0, in the control register, as detailed in table iii. when power supplies are first applied to the ad7904/ AD7914/ad7924, care should be taken to ensure that the part is placed in the required mode of operation (see the powering up the ad7904/AD7914/ad7924 section). normal mode (pm1 = pm0 = 1) this mode is intended for the fastest throughput rate performance as the user does not have to worry about any power-up times with the ad7904/AD7914/ad7924 remaining fully powered at all times. figure 11 shows the general diagram of the operation of the ad7904/AD7914/ad7924 in this mode. the conversion is initiated on the falling edge of cs and the track and hold will enter hold mode as described in the serial interface section. the data presented to the ad7904/AD7914/ad7924 on the din line during the first 12 clock cycles of the data transfer are loaded into the control register (provided write bit is set to 1). the part will remain fully powered up in normal mode at the end of the conversion as long as pm1 and pm0 are set to 1 in the write transfer during that same conversion. to ensure continued operation in normal mode, pm1 and pm0 must both be loaded with 1 on every data transfer, assuming a write opera- tion is taking place. if the write bit is set to 0, then the power management bits will be left unchanged and the part will remain in normal mode. sixteen serial clock cycles are required to complete the conver- sion and access the conversion result. the track and hold will go back into track on the fourteenth s clk falling edge. cs may then idle high until the next conversion or may idle low until sometime prior to the next conversion, (effectively idling cs low). once a data transfer is complete (dout has returned to three- state), another conversion can be initiated after the quiet time, t quiet , has elapsed by bringing cs low again. 1 12 cs sclk dout din 16 2 leading zeros + 2 channel identifier bits + conversion result data in to control register note: control register data is loaded on first 12 sclk cycles figure 11. normal mode operation full shutdown (pm1 = 1, pm0 = 0) in this mode, all internal circuitry on the ad7904/AD7914/ ad7924 is powered down. the part retains information in the control register during full shutdown. the ad7904/AD7914/ ad7924 remains in full shutdown until the power management bits in the control register, pm1 and pm0, are changed. if a write to the control register occurs while the part is in full shutdown, with the power management bits changed to pm0 = pm1 = 1, normal mode, the part will begin to power up on the cs rising edge. the track and hold that was in hold while the part was in full shutdown will return to track on the fourteenth sclk falling edge. to ensure that the part is fully powered up, t power up (t 12 ) should have elapsed before the next cs falling edge. figure 12 shows the general diagram for this sequence. auto shutdown (pm1 = 0, pm0 = 1) in this mode, the ad7904/AD7914/ad7924 automatically enters shutdown at the end of each conversion when the control register is updated. when the part is in shutdown, the track and hold is in hold mode. figure 13 shows the general diagram of the operation of the ad7904/AD7914/ad7924 in this mode. in shutdown mode all internal circuitry on the ad7904/AD7914/ad7924 is powered down. the part retains information in the control register during shutdown. the ad7904/AD7914/ad7924 remains in shutdown until the next cs falling edge it receives. on this cs falling edge the track and hold that was in hold while the part was in shutdown will return to track. wake-up time from auto shutdown is 1 s maximum, and the user should ensure that 1 s has elapsed before attempting a valid conver- sion. when running the ad7904/AD7914/ad7924 with a 20 mhz clock, one 16 sclk dummy cycle should be sufficient to ensure the part is fully powered up. during this dummy cycle the contents of the control register should remain unchanged, therefore the write bit should be 0 on the din line. this dummy cycle effectively halves the throughput rate of the part, with every other conversion result being valid. in this mode the power consumption of the part is greatly reduced with the part entering shutdown at the end of each conversion. when the control register is programmed to move into auto shutdown, it does so at the end of the conversion. the user can move the adc in and out of the low power state by controlling the cs signal.
ad7904/AD7914/ad7924 ?19? rev. 0 cs sclk dout din 114161 14 16 pa r t is in full shutdown pa rt begins to power up on cs rising edge as pm1 = pm0 = 1 the part is fully powered up once t power up has elapsed control register is loaded on the first 12 clocks. pm1 = 1, pm0 = 1 to keep the part in normal mode, load pm1 = pm0 = 1 in control register channel identifier bits + conversion result da ta in to control register da ta in to control register t 12 figure 12. full shutdown mode operation 1 cs sclk dout din 16 1161 16 dummy conversion channel identifier bits + conversion result invalid data channel identifier bits + conversion result da ta in to control register pa r t enters shutdown on cs rising edge as pm1 0, pm0 1 control register is loaded on the first 12 clocks, pm1 0, pm0 1 da ta in to control register control register contents should not change, write bit 0 to keep part in this mode, load pm1 0, pm0 1 in control register or set write bit = 0 pa r t is fully powered up pa rt begins to po wer up on cs fa lling edge pa r t enters shutdown on cs rising edge as pm1 0, pm0 1 12 12 12 figure 13. auto shutdown mode operation powering up the ad7904/AD7914/ad7924 when supplies are first applied to the ad7904/AD7914/ad7924, the adc may power up in any of the operating modes of the part. to ensure the part is placed into the required operating mode the user should perform a dummy cycle operation as outlined in f igures 14a through 14c. the dummy conversion operation must be performed to place the part into the desired mode of operation. to ensure the part is in normal mode, this dummy cycle operation can be performed with the din line tied high, i.e., pm1, pm0 = 1,1 (depending on other required settings in the control register) but the minimum power-up time of 1 s must be allowed from the rising edge of cs , where the control register is updated, before attempting the first valid conversion. this is to allow for the possibility that the part initially powered up in shutdown. if the desired mode of operation is full shutdown, then again only one dummy cycle is required after supplies are applied. in this dummy cycle the user simply sets the power management bits, pm1, pm0 = 1,0 and upon the rising edge of cs at the end of that serial transfer the part will enter full shutdown. if the desired mode of operation is auto shutdown after sup- plies are applied, then two dummy cycles will be required, the first with din tied high and the second dummy cycle to set the power management bits pm1 and pm0 = 0,1. on the second cs rising edge after the supplies are applied, the control regis- ter will contain the correct information and the part will enter auto shutdown mode as programmed. if power consumption is of critical concern, then in the first dummy cycle the user may set pm1, pm0 = 1,0, i.e., full shutdown, and then place the part into auto shutdown in the second dummy cycle. for illus- tration purposes, figure 14c is shown with din tied high on the first dummy cycle in this case. figures 14a, 14b, and 14c each show the required dummy cycle(s) after supplies are applied in the case of normal mode, full shutdown mode, or auto shutdown mode, respectively, being the desired mode of operation.
?20? ad7904/AD7914/ad7924 rev. 0 invalid data channel identifier bits + conversion result din line high for first dummy conversion da ta in to control register to keep the part in normal mode, load pm1 = pm0 = 1 in control register 114161 14 16 t 12 allow t power to elapse if in shutdown at power-on, pa rt begins to power up on cs rising edge as pm1 = pm0 = 1 pa r t is in unknown mode after power-on cs sclk dout din figure 14a. to place ad7904/AD7914/ad7924 into normal mode after supplies are first applied invalid data 11416 pa r t e n ters shutdown on cs rising edge as pm1 = pm0 = 0 pa r t is in unknown mode after power-on cs sclk dout din da ta in to control register control register is loaded on the first 12 clocks. pm1 = 1, pm0 = 0 figure 14b. to place ad7904/AD7914/ad7924 into full shutdown mode after supplies are first applied invalid data invalid data din line high for first dummy conversion da ta in to control register control register is loaded on the first 12 clocks. pm1 = 0, pm0 = 1 114161 14 16 pa r t is in unknown mode after power-on cs sclk dout din pa r t e n ters auto shutdown on cs rising edge as pm1 = 0, pm0 = 1 figure 14c. to place ad7904/AD7914/ad7924 into auto shutdown mode after supplies are first applied power versus throughput rate by operating in auto shutdown mode on the ad7904/AD7914/ ad7924, the average power consumption of the adc decreases at lower throughput rates. figure 15 shows how as the through- put rate is reduced, the part remains in its shutdown state longer and the average power consumption over time drops accordingly. for example, if the ad7924 is operated in a continuous sam- pling mode, with a throughput rate of 100 ksps and an sclk of 20 mhz (v dd = 5 v), and the device is placed in auto shut- down mode, i.e., if pm1 = 0 and pm0 = 1, then the power consumption is calculated as follows: the maximum power dissipation during normal operation is 13.5 mw (v dd = 5 v). if the power-up time from auto shut down is one dummy cycle, i.e., 1 s, and the remaining conversion time is another cycle, i.e., 1 s, then the ad7924 can be said to dissipate 13.5 mw for 2 s during each conversion cycle. for the remai nder of the conversion cycle, 8 s, the part remains in shutdown. the ad7924 can be said to dissipate 2.5 w for the remaining 8 s of the conversion cycle. if the throughput rate is 100 ksps, the cycle time is 10 s and the average power dissipated during each cycle is (2/10) (13.5 mw) + (8/10) (2.5 w) = 2.702 mw.
ad7904/AD7914/ad7924 ?21? rev. 0 figure 15 shows the maximum power versus throughput rate when using the auto shutdown mode with 5 v and 3 v supplies. throughput e ksps 10 0 100 200 300 power e mw 1 0.1 0.01 50 150 250 350 v dd = 5v v dd = 3v figure 15. ad7924 power vs. throughput rate serial interface figures 16, 17, and 18 show the detailed timing diagrams for serial interfacing to the ad7904, AD7914, and ad7924, respectively. the serial clock provides the conversion clock and also controls the transfer of information to and from the ad7904/AD7914/ad7924 during each conversion. the cs signal initiates the data transfer and conversion process. the falling edge of cs puts the track and hold into hold mode, takes the bus out of three-state and the analog input is sampled at this point. the conversion is also initiated at this point and will require 16 sclk cycles to complete. the track and hold will go back into track on the fourteenth sclk falling edge as shown in figures 16, 17, and 18 at point b. on the sixteenth sclk falling edge, the dout line will go back into three-state. if the rising edge of cs occurs before 16 sclks have elapsed, the conversion will be terminated, the dout line will go back into three-state, and the control register will not be updated; otherwise dout returns to three-state on the sixteenth sclk falling edge as shown in figures 16, 17, and 18. cs sclk dout din t 2 t 3 t 9 t 4 t 7 t 5 t 11 t 8 t q uiet t 6 t convert 12 3456 111213141516 three- state zero add1 add0 db7 db6 db0 zero zero zero zero three- state 4 trailing zeros 2 identification bits t 10 zero b write seq1 dontc dontc add1 add0 coding dontc dontc dontc dontc figure 16. ad7904 serial interface timing diagram cs sclk dout din t 2 t 3 t 9 t 4 t 7 t 5 t 11 t 8 t 6 t convert 12 345 6111213141516 three- state zero add1 add0 db9 db8 db2 db1 db0 zero zero three- state 2 trailing zeros 2 identification bits t 10 zero b write seq1 dontc dontc add1 add0 coding dontc dontc dontc dontc t q uiet figure 17. AD7914 serial interface timing diagram cs sclk dout din t 2 t 3 t 9 t 4 t 7 t 5 t 11 t 8 t 6 t convert 12 345 6111213141516 three- state zero add1 add0 db11 db10 db4 db3 db2 db1 db0 three- state 2 identification bits t 10 zero b write seq1 dontc dontc add1 add0 coding dontc dontc dontc dontc t q uiet figure 18. ad7924 serial interface timing diagram
?22? ad7904/AD7914/ad7924 rev. 0 sixteen serial clock cycles are required to perform the conversion process and to access data from the ad7904/AD7914/ad7924. for the ad7904/AD7914/ad7924 the 8/10/12 bits of data are preceded by two leading zeros and two channel address bits add1 and add0, identifying which channel the result corresponds to. cs going low clocks out the first leading zero to be read in by the microcontroller or dsp on the first falling edge of sclk. the first falling edge of sclk will also clock out the second leading zero to be read in by the m icrocontroller or dsp on the second sclk falling edge, and so on. the remaining two address bits and 8/10/12 data bits are then clocked out by subsequent sclk falling edges beginning with the first address bit add1; thus the second falling clock edge on the serial clock has the second leading zero provided and also clocks out address bit add1. the final bit in the data t ransfer is valid on the sixteenth falling edge, having been clocked out on the previous (fift eenth) falling edge. writing of information to the control register takes place on the first 12 falling edges of sclk in a data transfer, assuming the msb, i.e., the write bit, has been set to 1. the ad7904 will output two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 8-bit conversion result, and four trailing zeros. the AD7914 will output two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 10-bit conver- sion result, and two trailing zeros. the 16-bit word read from the ad7924 will always contain two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 12-bit conversion result. microprocessor interfacing the serial interface on the ad7904/AD7914/ad7924 allows the part to be directly connected to a range of many different microprocessors. this section explains how to interface the ad7904/AD7914/ad7924 with some of the more common microcontroller and dsp serial interface protocols. ad7904/AD7914/ad7924 to tms320c541 the serial interface on the tms320c541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the ad7904/AD7914/ad7924. the cs input allows easy inter- facing between the tms320c541 and the ad7904/AD7914/ ad7924 without any glue logic required. the serial port of the tms320c541 is set up to operate in burst mode with internal clkx0 (tx serial clock on serial port 0) and fsx0 (tx frame sync from serial port 0). the serial port control register (spc) must have the following setup: fo = 0, fsm = 1, mcm = 1, and txm = 1. the connection diagram is shown in figure 19. it should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the tms320c541 provides equidistant sampling. the v drive pin of the ad7904/AD7914/ad7924 takes the same supply voltage as that of the tms320c541. this allows the adc to operate at a higher voltage than the serial inter- face, i.e., tms320c541, if necessary. tms320c541 * ad7904/ AD7914/ ad7924 * clkx clkr dr dt fsx fsr v dd sclk dout din cs v drive * additional pins removed for clarity figure 19. interfacing to the tms320c541 ad7904/AD7914/ad7924 to adsp-21xx the adsp-21xx family of dsps are interfaced directly to the ad7904/AD7914/ad7924 without any glue logic required. the v drive pin of the ad7904/AD7914/ad7924 takes the same supply voltage as that of the adsp-218x. this allows the adc to operate at a higher voltage than the serial interface, i.e., adsp-218x, if necessary. the sport0 control register should be set up as follows: tfsw = rfsw = 1, alternate framing invrfs = invtfs = 1, active low frame signal dtype = 00, right justify data slen = 1111, 16-bit data-words isclk = 1, internal serial clock tfsr = rfsr = 1, frame every word irfs = 0 itfs = 1 the connection diagram is shown in figure 20. the adsp-218x has the tfs and rfs of the sport tied together, with tfs set as an output and rfs set as an input. the dsp operates in alternate framing mode and the sport control register is set up as described. the frame synchronization signal generated on the tfs is tied to cs , and as with all signal processing applica- tions, equidistant sampling is necessary. however, in this example, the timer interrupt is used to control the sampling rate of the adc, and under certain conditions equidistant sampling may not be achieved. the timer register, and so on, are loaded with a value that will provide an interrupt at the required sample interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to control the rfs and thus the reading of data. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transmit with tfs is given (i.e., ax0 = tx0), the state of the sclk is checked. the dsp will wait until the sclk has gone high, low, and high before transmission will start. if the timer and sclk values are chosen such that the instruction to transmit occurs on or near the rising edge of sclk, then the data may be transmitted or it may wait until the next clock edge. for example, if the adsp-2189 had a 20 mhz crystal such that it had a master clock frequency of 40 mhz, then the master cycle time would be 25 ns. if the sclkdiv register is loaded with the value 3, then a sclk of 5 mhz is obtained and eight master clock periods will elapse for every one sclk period. depending on the throughput rate selected, if the timer register was loaded with the value, say 803 (803 + 1 = 804), then 100.5 sclks will occur between interrupts and subsequently between transmit
ad7904/AD7914/ad7924 ?23? rev. 0 instructions. this situation will result in nonequidistant sam- pling as the transmit instruction is occurring on a sclk edge. if the number of sclks between interrupts is a whole integer figure of n, then equidistant sampling will be implemented by the dsp. ad7904/ AD7914/ ad7924 * adsp-218x * sclk dr rfs tfs dt v dd sclk dout cs din v drive * additional pins removed for clarity figure 20. interfacing to the adsp-218x ad7904/AD7914/ad7924 to dsp563xx the connection diagram in figure 21 shows how the ad7904/AD7914/ad7924 can be connected to the essi (synchronous serial interface) of the dsp563xx family of dsps from motorola. each essi (two on board) is operated in synchronous mode (syn bit in crb = 1) with internally generated 1-bit clock period frame sync for both tx and rx (bits fsl1 = 0 and fsl0 = 0 in crb). normal operation of the essi is selected by making mod = 0 in the crb. set the word length to 16 by setting bits wl1 = 1 and wl0 = 0 in cra. the fsp bit in the crb should be set to 1 so the frame sync is negative. it should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the dsp563xx provides equidistant sampling. in the example shown in figure 21 below, the serial clock is taken from the essi so the sck0 pin must be set as an output, sckd = 1. the v drive pin of the ad7904/AD7914/ad7924 takes the same supply voltage as that of the dsp563xx. this allows the adc to operate at a higher voltage than the serial interface, i.e., dsp563xx, if necessary. ad7904/ AD7914/ ad7924 * dsp563xx * sck srd std sc2 v dd sclk dout cs din v drive * additional pins removed for clarity figure 21. interfacing to the dsp563xx application hints grounding and layout the ad7904/AD7914/ad7924 have very good immunity to noise on the power supplies as can be seen by the psrr vs. supply ripple frequency plot, tpc 3. however, care should still be taken with regard to grounding and layout. the printed circuit board that houses the ad7904/AD7914/ ad7924 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be separated easily. a minimum etch technique is generally best for ground planes as it gives the best shielding. all three agnd pins of the ad7904/AD7914/ad7924 should be sunk in the agnd plane. digital and analog ground planes should be joined at only one place. if the ad7904/AD7914/ad7924 is in a system where multiple devices require an agnd to dgnd connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the ad7904/AD7914/ad7924. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7904/AD7914/ad7924 to avoid noise coupling. the power supply lines to the ad7904/ AD7914/ad7924 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals, like clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. avoid crossover of digi- tal and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum in parallel with 0.1 f capacitors to agnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. the 0.1 f capacitors should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types or surface mount types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. evaluating the ad7904/AD7914/ad7924 performance the recommended layout for the ad7904/AD7914/ad7924 is outlined in the evaluation board for the ad7904/AD7914/ad7924. the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the pc via the eval- board controller. the eval-board controller can be used in conjunction with the ad7904/AD7914/ad7924 evaluation board, as well as many other analog devices evaluation boards ending in the cb designator, to demonstrate/evaluate the ac and dc performance of the ad7904/AD7914/ad7924. the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the ad7904/AD7914/ ad7924. the software and documentation are on a cd shipped with the evaluation board.
c03087?0?11/02(0) printed in u.s.a. ad7904/AD7914/ad7924 ?24? rev. 0 outline dimensions 16-lead thin shrink small outline package (tssop) (ru-16) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153ab

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